Prerequisites - part 2

Prerequisites - part 1 Digital fundamentals

Let's dive into the prerequisites for ASIC design.

We will discuss Digital Electronics Fundamentals (Combinational gates, Sequential circuits), Verilog Fundamentals, RC Circuits and CMOS fundamentals (operation, characteristics and Fabrication process).

Digital Electronics Fundamentals:

Digital Signal:

Binary system: a number system that has only two possible values for each digit: 0 and 1

decimal	binary	Bit
0	0	1 bit
1	1
2	10	2 bit
3	11
4	100	3 bit
5	101
6	110
7	111
8	1000	4 bit

 

And so on

Combinational Gates: 

• Output depends only on the present inputs.
• Speed is fast
• Easily designed.
• No feedback between input and output
• Time independent
• Elementary building blocks (AND, OR, NAND, NOR, XOR, XNOR MUX etc.)
• NAND and NOR are universal gates.
• Used for both arithmetic and boolean operations.

Applications

• ALU (comparators, programmable logic devices, adder and subtractor)
• Data transmission Circuits (Parallel to serial converters, Data routing, Serial to Parallel converters, Bit compression, ADC & DAC, Encoder and Decoder)
• Code converter circuits

Advantages:

• simplicity
• no delay
• predictable and repeatable results

Disadvantages:

• limited functionality
• less flexibility
• complexity in large designs

Sequential Gates:

• Output depends on both present input and previous output.
• This includes memory elements with combinational circuits
• The memory elements are capable of storing binary information. (Latches and flipflops)

Applications:

• Shift Registers,
• Flip Flop
• ADC and DAC
• Counters     
• Clocks
• Registers inside microprocessors and controllers to store temporary information.
• applied in programmable devices like CPLD, PLD and FPGA

Advantages:

• Memory: store and process data in a specific order (timer and counters)
• Error detection: detects errors in data or instructions, thereby improving reliability.
• Timing: implement timing and synchronization for real-time control.

Disadvantages:

• complex and require more effort to implement.
• consume more power than combinational circuits.
• challenging due to the need to ensure that the timings of the input and outputs are correct.

 

ASIC design flow

This blog attempts to explain different steps in the ASIC design flow, starting from the ASIC design concept and how and why it is needed. The blog aims to provide a short and precise explanation of the concept phase.

What is ASIC design?

An ASIC, or Application-Specific Integrated Circuit, is a type of integrated circuit designed to perform a specific function or task. They are designed to deliver better performance, power efficiency and cost-effectiveness for the intended task. 

Before diving into the nitty-gritty of ASIC design, let's walk through the steps together. It's going to be an exciting journey!

What are the different stages of ASIC design flow?

 

Specification: Received from the customer’s end.

Architecture: Divide a large system into blocks.

Front end:

1. Coding: Enter the design into an ASIC design system using a hardware description language (HDL). This job is done by an RTL (Register Transfer Level) design engineer.
2. Functional Verification: Check to see if the design functions correctly. This job is performed by a verification engineer.

Back end:

1. Logic synthesis: Use an HDL (VHDL or Verilog) and a logic synthesis tool to produce a netlist —a description of the logic cells and their connections.
2. DFT (Design for testability): Technique to make testing a chip possible and cost-effective by adding additional circuitry to the design. This task is performed by DFT engineers.
3. Place and Route (PNR): Arrange the blocks of the netlist on the chip. Decide the locations of cells in the block. Make the connections between cells and blocks. Determine the resistance and capacitance of the interconnect. This task is performed by PNR engineers (also known as PDEs/Physical Design Engineers)
4. Sign-off and tape out: Check to see if the design still works with the added loads of the interconnect and is ready for manufacturing. This task is divided and performed by various engineers. (Timing sign-off is done by STA engineers, Power sign-off is done by IR/PDN sign-off engineer, physical sign-off engineer is done by PV (physical verification) engineer)

     Finished product:
     In the last stage, once tape-out is done, the engineer performs wafer processing, packaging, testing, verification and delivery to the physical IC. GDSII is the file produced and used by the semiconductor foundries to fabricate the silicon and hand it to the client.

 Why do we need an ASIC design flow?

      To ensure successful ASIC design, engineers must follow a proven ASIC design flow, which is based on a good understanding of ASIC specifications, requirements, low-power design, and performance, with a focus on meeting the goal of the customer. Every stage of the ASIC design cycle has EDA tools that can help to implement ASIC design with ease.

What are the advantages of ASICs?

• ASICs are designed to perform specific tasks, which means they are optimized to deliver high performance as well.

• They enable the use of multiple functions and components, reducing the complexity and size of the design.

• AICS offer a high level of customization, letting the designer mould the chip to meet the requirements.

• ASICs are a reliable choice for mission-critical applications. Their specialized design and integrated components on a single chip guarantee improved reliability compared to off-the-shelf components.

• ASICs reduce EMI and improve system performance by integrating multiple components on a single chip while meeting regulatory standards.

• ASICS consume less power due to their specialized nature.
• The initial development can be high, but the cost significantly decreases once the chip is produced in large volume.

Where do we apply ASICs?

The area of applications of ASICs is where there is a need for performance, customization and size. Some of the examples are mentioned below.

• Sensors and Transducers
• Automotive and Avionic Components (electronic system used in aircraft)
• Satellite, Radar and Communication-related processors
• Microprocessors, Memories, Microcontrollers

What are the EDA tools available for implementing ASIC design?

company	Tool	purpose
Cadence Design System	Xcelium	RTL Simulations
	NC-Sim
	Incisive
	JasperGold	RTL Signoff
	Genus Synthesis Solution	Logic Synthesis
	RTL Compiler (upgraded to Genus)
	Conformal	Logical Equivalence Check
	Innovus	Place and Route
	Encounter (upgraded to Innovus)
	Quantus RC Extraction	RC Extraction
	Tempus	Static Timing Analysis
	Encounter Timing System (ETS)
	Voltus	IR analysis
	Pegasus	Physical Verification
	PVS (Physical Verification System)
	Jules	Power simulation
Synopsys	VCS	RTL Simulations
	SpyGlass	RTL Signoff
	Fusion Compiler (RTL-to-GDSII solution)	Logical Synthesis
	Design Compiler
	Formality	Logical Equivalence Check
	IC Compiler (ICC)	Place and Route
	StarRC	RC Extraction
	primeTime	Static Timing Analysis
	Tweaker (Dorado, now part of synopsys)
	IC Validator	Physical Verifications
Mentor Graphics (Acquired by Siemens in 2017,now known as Siemens EDA)	QuestaSim	RTL Simulations
	ModelSim
	Calibre	Physical verifications
Ansys	Totem	Power integrity and reliability sign off
	Redhawk
Xilinx (Acquired by AMD in 2022)	ISE Simulator	RTL Simulations